In wireless telecommunication systems the transmit signal typically occupies a well-defined part of the frequency spectrum and power emitted outside this frequency range is subject to maximum emission limits imposed by regulatory or other requirements. These requirements ensure communication equipment using different parts of the frequency spectrum do not excessively interfere with one another.
The 3GPP (3rd Generation Partnership Project) specification for E-UTRA (evolved-UMTS Terrestrial Radio Access), better known as LTE (Long Term Evolution), now list 38 different frequency bands for use by the latest generation of cellular communication equipment. Many of these bands are located in close vicinity to each other or to frequency bands of incumbent technologies such as television broadcast.
In a number of cases out-of-band emissions are restricted to very low levels just outside the allocated frequency bands. One example of particular interest relates to emissions from LTE band 13 (transmit band at 777 MHz to 787 MHz) into a US public safety band (between 769 MHz and 775). Another example is emissions from LTE band 1 (transmit band at 1920 MHz to 1980 MHz) into the PHS (Personal Handy-phone System) band which is in use in Japan, China, Taiwan and some other Asian countries, and which uses spectrum up to 1930 MHz.
Stringent emission limits that apply just a few megahertz outside the desired transmit channel impose a number of challenging design constraints on the transmitter architecture. FIG. 1 shows a simplified block diagram of a representative architecture of a state-of-the-art LTE transmitter. The user data is interleaved with control data (omitted in the diagram) and modulated using a technique called SC-FDMA (Single-Carrier FDMA) which yields a stream of time-domain data symbols. Between these symbols a cyclic prefix is inserted to effectively create a guard time between the data symbols. At this point in the signal chain the frequency spectrum associated with the data stream is not very well confined to the desired bandwidth and is shaped by digital filtering to reject unwanted out-of-band emissions. Typically, the data stream is then up-sampled to a rate multiple times the native LTE symbol rate which by the process known as aliasing again produces unwanted out-of-band emissions. These can be removed using the anti-aliasing filter shown in FIG. 1.
The signal can then be converted from the digital into the analog domain using a DAC. The radio topology shown is known as a zero-IF architecture where the complex baseband signal is represented by two real-valued signal paths (I and Q) in the analog domain. This type of architecture is very common in low-cost transceiver designs based on CMOS technology.
Following the DAC the signal is filtered again, mainly to remove DAC quantization noise at the duplex offset for FDD radio bands. Then, the I and Q signal paths are jointly up-converted onto an RF carrier in the IQ modulator block. The resulting RF signal is then amplified and filtered again before being transmitted from the antenna.
The previously-discussed emission limits set design constraints on a number of blocks shown in the architecture in FIG. 1. For example, the combination of pulse shaping, digital anti-aliasing filter and analog reconstructing filter must suppress out-of-band power at the critical frequency offsets adequately so they make negligible contribution to out-of-band noise after up-conversion to RF and RF amplification. Furthermore, all blocks in the analog and RF signal path must be linear enough to avoid spectral re-growth products violating the out-of-band emission limits. This is of particular importance to wide transmit signal allocations where the distance between allocated transmit channel and protected frequency band is less that the bandwidth of the signal and third-order intermodulation products are critical.
For LTE in particular, there is also another important case which drives the linearity constraints of the IQ modulator. Assume a narrow transmit signal (narrow resource block allocation in case of LTE) at some offset corresponding to angular frequency ΩIF from the carrier with angular frequency ΩLO. For simplicity, we assume the transmit signal at offset ΩIF is a pure tone represented by the two baseband voltagesVI=A·cos(ΩIF·t) andVQA·sin(ΩIF·t).The baseband signal path is typically realized using differential circuitry which has almost negligible even-order non-linearity. However, assume a degree of odd-order non-linearity which can be expressed as a polynomial of the form Vout=c1·Vin+c3·Vin3+c5·Vin5+ . . . .Using the complex tone as an input signal Vin yields the following output signals:Vout, I=A·(c1+¾c3+⅝c5+ . . . )·cos(ΩIF·t)+A3·(+¼c3+ 5/16c5+ . . . )·cos(3·ΩIF·t)+A5·(+ 1/16c5+ . . . )·cos(5·ΩIF·t)+  (1)Vout, Q=A·(c1+¾c3+⅝c5+ . . . )·sin(ΩIF·t)+A3·(−¼c3− 5/16c5+ . . . )·sin(3·ΩIF·t)+A5·(+ 1/16c5+ . . . )·sin(5·ΩIF·t)+  (2)When (1) and (2) are up-converted to RF in a quadrature mixer and summed, the resulting spectrum contains frequency products at odd harmonics of the input tone. The tones appear only on one side of the carrier due to the image cancellation occurring in the summation stage of the IQ modulator.
The resulting spectrum is shown in FIG. 2, which shows the spectrum at RF output. Odd-order non-linearity in the IQ modulator creates unwanted out-of-band products at frequency offsets corresponding to odd multiples of the input signal frequency offset from carrier.
The rejection of the third-order product at ΩLO−3·ΩIF, which we shall refer to as LOIM3, is given by the ratio 16 c12/c32. Third-order nonlinearity is often determined and chararacterized by passing two tones of equal amplitude through a nonlinear system and measuring the rejection between unwanted intermodulation product and wanted tones. By comparison, that rejection, normally referred to as IM3, is given by IM3=16/9·c12/c32.
For LTE band 13 support of a narrow RB allocation at full power requires a rejection of the unwanted tone by at least 66 dB with respect to the wanted tone to meet emission specs for the public safety band. It turns out that this requirement is much more stringent than the general linearity requirement derived from mask, ACLR (adjacent channel leakage ratio) or EVM (error vector magnitude) specifications.
For baseband gain and filter stages the required linearity can be achieved relatively easily but for IQ modulator the target figure represents a serious design challenge.
The 3GPP specification for the critical LTE bands allows reduction of transmitter output power for the most challenging out-of-band emission scenarios. This automatically reduces the effect of non-linearity but also reduces the transmit range of the device. It is therefore highly desirable to meet the out-of-band emission specifications even at maximum allowed output power by dedicated design.
Conceptually the most straight-forward way of reducing out-of-band emissions is to employ filtering of the signal in the RF front-end after the power amplifier just before the signal is coupled into the antenna. Recent advancements of SAW and FBAR technology have made it possible to achieve significant rejection of unwanted out-of-band power just a few megahertz away from the band edge. However, even the most sophisticated filters are not able to fully reject the discussed narrow-band signals in case of LTE bands 13 and band 1. Often, a second RF filter is added before the signal is amplified in the power amplifier to clear up unwanted frequency products in the transmit chain which increases the cost and footprint of the overall solution.
To improve the linearity of the mixer, a well-known technique is to use active current-driven mixer topologies (known as Gilbert mixers) where the input current is linearized through a feedback-loop in the transconductor stage. In that topology, negative feedback is created using an operational amplifier, the penalty being that the modulator is now noisy and will not meet the Rx-band noise requirements for LTE FDD bands.
Finally, it is possible to correct for non-linearity occurring in the analog signal path by applying pre-distortion in the digital domain. This technique requires characterization or possibly product-level calibration to find the correct parameters necessary to cancel the unwanted frequency products. It also adds significantly to overall complexity of the solution as the pre-distortion, digital filtering, analog filtering and analog non-linearity all interact in a non-trivial way.
FIG. 3 shows a simplified block diagram of a passive Transmit (Tx) IQ Modulator, essentially a voltage-mode passive mixer used with 25% duty-cycle local oscillator (LO) I and Q waveforms used, to realize the I+jQ summation in voltage mode at RF. Analytical analysis shows that the conversion loss is at best 2√2/π or −0.9 dB.
We have selected a passive mixer as this general type of mixer exhibits extremely low noise. The dominant noise source is thermal noise of switch on-resistance, which can be as low as 0.575 nV/√Hz for 20Ω switch on-resistance. Such mixers are also as linear as the switches used within them, with nMOS and CMOS (transmission gate) switches commonly used. It should be noted that in the context of a switch, non-linearity is expressed as the deviation from constant resistance with the magnitude of signal passing through the switch in its on state. Thus a truly linear switch has constant on-resistance regardless of the magnitude of a signal carried.
The time-varying I and Q input signals Vin, IP, Vin, IN, Vin, QP and Vin, QN are periodically sampled by the clock signals φ1, φQ, φI′ and φQ′. The clock signals are periodic with an angular frequency ΩLO.
In a specific embodiment, the clock signals are arranged such that they have roughly 25% duty cycle which means only one pair of switches is on at any moment in time and the other three pairs of switches are off. The use of 25% duty cycle has a number of advantages such as improved conversion gain and reduced mixer noise figure. The clock signals are illustrated in FIG. 4.
As explained above, any switch non-linearity will get modulated onto the sampled input waveform thereby creating undesirable IF harmonics which are then up-converted to RF. The most problematic harmonic is the third harmonic, which appears at RF with an angular frequency ΩLO−3·ΩIF. Higher order products also exist but they are generally less problematic than the aforementioned third-order product.
Consider just one of the eight switches in FIG. 3. Typically, this switch function is realized using a pMOS or nMOS device or a CMOS switch as mentioned above, with the latter preferred as a result of its higher dynamic range and the fact that charge injection can be reduced by dimensioning the complementary devices equally (this is further expatiated below). Equation 3 gives the CMOS switch on-resistance Rswitch to the first-order.
                              R          switch                ≅                  1                                                    K                n                            ⁢                              W                L                            ⁢                              (                                                      V                    gsn                                    -                                      V                    Tn                                                  )                                      +                                          K                p                            ⁢                              W                L                            ⁢                              (                                                      V                    sgp                                    -                                                                                V                      Tp                                                                                          )                                                                        (        3        )            Here, Kn and Kp are process-dependent constants relating to the transconductances of the transistors, W and L are the width and length of the transistors, respectively, Vgsn is the gate-source voltage of the nMOS, Vsgp is the source-gate voltage of the pMOS and VTn and VTp are the threshold voltages of the two devices, respectively. In this case the values of Vgsn and Vsgp both depend on the input voltage level, Vin.
Hence, even in the first order approximation (3), the on-resistance of the transmission gate is a function of the input voltage when in an on-state; this is the root-cause for mixer nonlinearity. The gate-to-channel capacitances are also non-linear and input-dependent, contributing even further to the sampling distortion but can be minimized or even eliminated by connecting the devices' bulk terminal to the source terminal (possible for the nMOS device if a twin-tub process technology is available) and by using non-overlapping clocks which also minimizes the effect of the gate-to-source/drain parasitic capacitances.
FIG. 5 depicts the non-linear sampling switch in sampling mode. It is shown to have a main current path with a variable series resistance (RS1) variable with gate source voltage (Vgs), a gate-source capacitance (Cgs) a gate-drain capacitance (Cgd) and a capacitor (C1) in series with the main current path representing RF amplifier gate capacitance.
The s-domain transfer function from the sampled input to the bottom plate of C1 under sampling conditions with the parasitic capacitances neglected is given by equation 4:
                                                        V                              C                ⁢                                                                  ⁢                1                                                    V              in                                ⁢                      (            s            )                          =                  1                      1            +                          s              ⁢                                                          ⁢                              C                1                            ⁢                              R                                  S                  ⁢                                                                          ⁢                  1                                                                                        (        4        )            Substituting (3) in (4) and recognizing that Vgs for switch S1 is given by Vgs=Vg−Vin, equation (5) results in the following expression:
                                                        V                              C                ⁢                                                                  ⁢                1                                                    V              in                                ⁢                      (            s            )                          =                                                            K                n                            ⁢                              W                L                            ⁢                              (                                                      V                    gn                                    -                                      V                    Tn                                    -                                      V                    in                                                  )                                      +                                          K                P                            ⁢                              W                L                            ⁢                              (                                                      V                    in                                    -                                      V                    gp                                    -                                                                                V                      Tp                                                                                          )                                                                                                                                                    K                      n                                        ⁢                                          W                      L                                        ⁢                                          (                                                                        V                          gn                                                -                                                  V                          Tn                                                -                                                  V                          in                                                                    )                                                        +                                                                                                                                                K                      p                                        ⁢                                          W                      L                                        ⁢                                          (                                                                        V                          in                                                -                                                  V                          gp                                                -                                                                                                        V                            Tp                                                                                                                        )                                                        +                                      sC                    1                                                                                                          (        5        )            Rearranging (5) gives a non-linear expression of Vin as equation 6:
                                          V                          C              ⁢                                                          ⁢              1                                ⁡                      (            s            )                          =                                                                              K                  n                                ⁢                                  W                  L                                ⁢                                  (                                                            V                      gn                                        -                                          V                      Tn                                        -                                          V                      in                                                        )                                            +                                                K                  p                                ⁢                                  W                  L                                ⁢                                  (                                                            V                      in                                        -                                          V                      gp                                        -                                                                                        V                        Tp                                                                                                    )                                                                                                                                                                        K                        n                                            ⁢                                              W                        L                                            ⁢                                              (                                                                              V                            gn                                                    -                                                      V                            Tn                                                    -                                                      V                            in                                                                          )                                                              +                                                                                                                                                                  K                        p                                            ⁢                                              W                        L                                            ⁢                                              (                                                                              V                            in                                                    -                                                      V                            gp                                                    -                                                                                                                V                              Tp                                                                                                                                  )                                                              +                                          sC                      1                                                                                                    ·                                    V              in                        .                                              (        6        )            
A problem then focuses on how to provide a highly linear switch usable in a mixer, and capable of being used in such a mixer for an LTE device. Such a switch would of course be usable in other applications to good effect, and would not be limited to mixer application.
Various methods have been employed in the past to address this issue. The simplest is an arbitrary increase of the aspect ratio of the device until the on-resistance error term with varying input is small enough to be negligible. This is unsuitable for high-speed designs.
Employing low threshold voltage devices in 1.2V 65 nm process-node is also not sufficient to address this issue.